A conventional clock-data recovery (“CDR”) module of multi-gigabit serial data transceiver may align a clock to a median position of edges of a waveform after equalization. Data may be sampled a fixed time after this median position is aligned to a clock, such as at one-half of a bit period. However, this sample point may be less than optimal due to one or more of: (a) variations in the clock distributions between edge samplers and a data sampler may move a data sample point relative to an equalized waveform unpredictably; and (b) characteristics of a communication channel or an equalization skew of edge distributions may change unpredictably, inducing low probability bit errors on a long tail of such skewed distributions.
Hence, it is desirable and useful to provide sampling that increases margin for recovering data.